This invention relates to a communication system in which an arbitrary number of control stations (hereinafter referred to simply as modules) are connected to a serial transmission path which is a single loop communication path.
A prior art communication system, in which a plurality of control stations are connected to a loop, has been provided with both a master station and slave stations. An example is seen in U.S. Pat. No. 4,136,384 and in the article "system design of the distributed double-loop computer network (DDLCN)" by Ming T. Liu et al, Dept. of Computer and Information Science, The Ohio State University, Columbus, Ohio 43210, 1979, IEEE. This prior art loop communication system with a master station and slave stations has a construction such as shown in FIGS. 1 and 2. That is, process input-output stations 3 are connected to a loop communication path, which is provided in the form of a serial bus 1, through communication control stations 2. Operators 3A and sensors 3B, etc. are connected to the stations 3. A control or master station 4 is connected to the serial bus 1. The above-mentioned process input-output stations 3 are slave stations of the control station 4. The communication controlling stations 2 to which the control station 4 and the process input-output stations 3 are connected has a construction such as shown in FIG. 2. That is, in the control station 4, a repeater or a wave form shaping circuit 5 and a stand-by control station (back-up station) 19 are selectively connected to the loop communication path 1 through a switch S1. The loop communication path 1 is connected to the output terminals of the repeater 5 and the stand-by control station 19 through another switch S2. The input and output switches S1 and S2, respectively, are usually connected to the repeater 5. The control station 4 is so constructed that a signal entering the input of the repeater 5 is introduced into both a 8-bit buffer 6 and a GA detection circuit 9 which detects a GA (go ahead) signal or a signal having a transmission right. A timer 10 is connected to the GA detection circuit 9. An abnormal state detecting circuit 11 and a GA generation circuit 7 are connected to the timer 10. It is so constructed that an oscillation signal from a clock oscillator 8 is supplied to the GA generation circuit 7, the output terminal of which is connected to the output of the repeater 5 through a switch. This switch has such a structure that switching to the 8-bit buffer 6 can also be effected. The switching is effected by an output signal from the timer 10. The switches on the input and output sides of the repeater 5 make a connection with the stand-by control station 19 when the abnormal state detecting circuit 11 operates. The repeater 5, the 8-bit buffer 6, the GA generation circuit 7, the oscillator 8, the GA detection circuit 9, the timer 10, the abnormal state detecting circuit 11 and the stand-by control station 19 constitute the control station 4.
Furthermore, the input of a repeater 5 in the communication controlling station 2 is connected to the loop communication path 1 through a switch, while the output of this repeater 5 is connected to the loop communication path 1 through a switch. A communication controlling LSI 12 and a clock synchronization circuit 13 are connected to the repeater 5. The station 2 is so constructed that a signal from the clock synchronization circuit 13 enters the communication controlling LSI 12, which is connected to a microprocessor unit MPU 14 by means of a data bus. A ROM 15, a RAM 16 and input-output interface LSI's 17A and 17B are connected to the MPU 14 through respective buses. A process input-output station 3 is connected to the input-output interface LSI 17A through a bus line. Further, an address setting switch 18 is connected to the input-output interface LSI 17B through a bus line. The communication controlling LSI 12, the clock synchronization circuit 13, the MPU 14, the ROM 15, the RAM 16, the input-output interface LSI 17, the address setting switch 18 and the repeater 5 constitute the communication controlling station 2. The controlling station 4 constructed in this manner monitors whether the GA signal passes in a pattern with an interval or is interrupted by some cause such as noise. Usually, a signal which is introduced into the repeater 5 from the loop communication path 1 through the switch is amplified by the repeater 5 and applied to the 8-bit buffer 6 and the GA detecting circuit 9. The GA signal amplified by the repeater 5 is detected by the GA detecting circuit 9, which resets the timer 10. The reset means that, if the GA signal is detected, the timer is cleared to "zero". If the count value becomes abnormally large, the abnormal state detecting circuit 11 detects this.
In the communication controlling station 2, a signal transferring from the serial bus or the loop communication path 1 is amplified by the repeater 5 and introduced into the communication controlling LSI 12 and the clock synchronization circuit 13.
As described above, the communication control in the conventional communication system has been performed as a master-slave type. That is, in such a system, the control station 4 which is a master station (primary station) controls the GA signal as well as the loop communication path 1, or the transmission path, simultaneously. Therefore,
(1) Since the communication system is of a master-slave type, the control station which is a master station (primary station) becomes a bottle neck against an increase of reliability. Namely, if trouble occurs in the master station, the whole communication to slave stations becomes impossible.
(2) Since the control station, or the master station 4, is provided without regard to the number of modules 2 which are provided, two kinds of modules for the master and slave stations, as shown in FIG. 2, are necessary. This has been a cause for preventing standardization (unification) of modules.